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[Other resource] xsoc-beta-093

Description: This free cpu-ip! use verilog
Platform: | Size: 3341210 | Author: 王军 | Hits:

[Other] jtag_verilog

Description: verilog 实现的jtag ip模块 包括了测试程序-Verilog achieve the JTAG ip modules including test procedures
Platform: | Size: 6047 | Author: 陈俊 | Hits:

[Other resource] ethernet.tar

Description: 以太网10/100M IP核Verilog源码，可综合。-IP Ethernet 10/100 nuclear Verilog source can be integrated.
Platform: | Size: 934772 | Author: 箫勇天 | Hits:

[mpeg mp3] video_compression_systems

Description: 根据jpeg标准用verilog语言编写的视频编码器，此编码器可作为一个通用IP使用，完成数字音频/视频的编解码功能-under jpeg standards with the Verilog language video encoder, this encoder can be used as a common IP use, complete digital audio / video codec
Platform: | Size: 222770 | Author: 崔云飞 | Hits:

[Crack Hack] aes_core

Description: AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use, developers can reduce design time.
Platform: | Size: 79788 | Author: 崔崔 | Hits:

[Other resource] ARM_Core

Description: arm verilog hdl ip core-arm Verilog HDL core ip
Platform: | Size: 71037 | Author: lile | Hits:

[Other resource] AUDIO_DAC

Description: 一个关于声音处理的Verilog语言编写的解码芯片，可以用于FPGA处理芯片的IP核，欢迎大家来用。-a voice on the Verilog language decoder chip, FPGA can be used to handle IP core chips, all are welcome to use.
Platform: | Size: 2009 | Author: 赵春生 | Hits:

[Other resource] USB2.0IP_core_Verilog

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Platform: | Size: 206883 | Author: 张清平 | Hits:

[Other resource] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit -
Platform: | Size: 359836 | Author: 任学 | Hits:

[Other resource] my_ip_core

Description: 在quartusII下用verilog语言自己写的IP核，对FPGA开发初学者有帮助的。-in quartusII verilog using their own language to write the IP core, FPGA development beginners to help.
Platform: | Size: 51070 | Author: 刘海 | Hits:

[Other resource] CAN_IPCore

Description: CAN_IPCore CAN协议的IP核源代码 verilog 语言
Platform: | Size: 61430 | Author: maliang | Hits:

[Other resource] Ethernet_verilog_ip_core

Description: Ethernet(以太网)verilog ip core用verilogHDL语言写的以太网软核，对学习verilog语言和以太网有很大帮助。
Platform: | Size: 903918 | Author: houlongting | Hits:

[Other resource] arm9_fpga2_verilog

Description: arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核，对学习arm和FPGA开发有帮助。
Platform: | Size: 195948 | Author: houlongting | Hits:

[VHDL-FPGA-Verilog] iir_2n_ip_float_demo

Description: 使用altera提供的ip核，实现了浮点数运算的2阶iir滤波器，结果与matlab运算结果相同。(Using the IP core provided by Altera, the 2 order IIR filter of floating point operation is implemented, and the result is the same as that of MATLAB operation.)
Platform: | Size: 48926720 | Author: 小天夫斯基 | Hits:

[VHDL-FPGA-Verilog] at7_ex04

Description: 通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and integrate as the IP kernel with Vivado.)
Platform: | Size: 1833984 | Author: 24fh | Hits:

[VHDL-FPGA-Verilog] FIR设计实现sgh

Description: FIR滤波FPGA实现 ，已在仿真软件上验证实现，不是IP核，不是ip核。(FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.)
Platform: | Size: 25600 | Author: 韩冻少 | Hits:

[VHDL-FPGA-Verilog] PLL

Description: 本次的设计主要任务是学会调用锁相环 IP 核，并对其进行仿真， 具体要求如下：（1）熟练掌握调用锁相环 IP 核的详细步骤。将 50M 的时钟分成 20MHz 和 100MHz 两个时钟（2）对锁相环进行仿真，验证 调用的锁相环的正确性。(The main task of this design is to learn to call the phase-locked loop IP core.)
Platform: | Size: 218112 | Author: 小猪仔521 | Hits:

[VHDL-FPGA-Verilog] tcp_ip_core_w_dhcp_latest.tar

Description: 以太网协议 TCP/IP/DHCP协议verilog实现(Ethernet IP/TCP/DHCP verilog source code)
Platform: | Size: 152576 | Author: 翾飞FEI | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:

[Embeded-SCM Develop] cordic

Description: 该程序实现了Cordic算法，未调用IP核通过Cordic算法进行三角函数运算(This program implements Cordic algorithm and does trigonometric function operation through Cordic algorithm without calling IP core.)
Platform: | Size: 2704384 | Author: 小明d1 | Hits:
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